The present invention relates to a disk array which attempts to increase data transfer speed and data faults by connecting a plurality of the disk apparatus in parallel to control the entire system, and more specifically, it relates to a control apparatus and the like, which are used for a disk array.
In order to improve processing capacity for a writing/reading request from a host computer, a disk array executes a large number of writing/reading processes (hereinafter, referred to as I/O process) simultaneously. To realize this, it is often the case that the disk array performs multitask processes by using a real time OS and the like on firmware (see Japanese Patent laidopen No 5-287849 and Japanese Patent laidopen No 5-298122, for example) . The multitask process is a process in which a plurality of tasks (modules for executing some series of processes) operate independently and, at the same time, a large number of tasks operate, thereby improving a processing capacity. According to this multitask process, since each task may execute one I/O process or a plurality of tasks can simultaneously execute a given I/O process, the rate of I/O processing capacity per unit of time is improved. In general, the multitask process with the real time OS is allowed to execute a plurality of tasks simultaneously by having a control memory area for each task in a local memory.
On the other hand, in the disk array of recent years, an attempt has been made to improve the performance by mounting a processor cache memory on a processor. That is, when access is repeatedly provided to the same memory area of the local memory, the data (such as micro programs, control information and the like) are held on the processor cache memory, which is fast in access speed. From the second access onward, the data on the processor cache memory is used. In this way, since the frequency of access to the local memory is reduced, processing speed of the processor is improved. As for a storage system of the data to the processor cache memory, a LRU (Least Recently Used) system is used in general. When there is no block available for storing data in the processor cache memory, the LRU system pages out that data block for which the longest time has elapsed since its most recent access.
In a multitask process, a memory area is allocated to every task. The memory area allocated to a task is named task memory. Accordingly, all the task memories can be stored within the processor cache memory when the number of tasks is small. Therefore, since it is sufficient for the processor to access only to the processor cache memory, the processor can process data at high speed. However, since the disk array is required to multi-execute the I/O process requests from a host computer, it is necessary that a large number of tasks are executed simultaneously to improve I/O processing speed. On the other hand, all the task memories cannot be stored within the processor cache memory when the number of tasks becomes large and, therefore, the paging out occurs frequently. This leads to lowering the processing speed of the processor. That is, there is a trade-off between the I/O processing speed and the processing speed of the processor. The trade-off for situations where a cache hit of a disk cache memory occurs and a cache miss hit occurs is described below. Note that the disk cache memory is a memory to hold data that are often used among data written/read from the host computer for the disk apparatus.
When there exists accessed data within the disk cache memory of the disk array when a reading request from the host computer is made, namely when “cache hit” occurs, there is no need to access to the disk apparatus and, therefore, there is no need to consider the I/O processing speed. Accordingly, it is effective to decrease the number of tasks so as to improve the processing speed of the processor.
On the other hand, when the data is read from the disk apparatus because the requested data is not within the disk cache memory, namely when a “cache miss hit” occurs, since it takes long time to execute one I/O process, it is necessary that the number of tasks is sufficient to improve overall I/O processing speed.
In this way, when the number of tasks is decreased in order to improve the processing speed of the processor upon a cache hit, the I/O processing speed upon a cache miss is lowered. On the other hand, when the number of tasks is increased contrariwise to improve the I/O processing speed upon a cache miss, the processing speed of the processor ends up being lowered upon a cache hit.